Method and arrangement for generating tracing signals

ABSTRACT

Tracing signals are applied to control the vertical and horizontal deflecting electrodes for a display or recording device to reproduce two-dimentional characters or indicia. In order to generate such tracing signals, the arrangement is provided with a memory which stores the programs which comprise two kinds of information, one being for setting the counters and the other being for counting input pulses up or down by the counters connected to the memory. The stepwise output of each of the counters is converted by the digital-to-analog converters into analog quantities to generate tracing or control voltages to be applied to the deflecting electrodes of the display or recording device.

United States Patent Sheftelman ..340/324 TO DA CONVERTER 26 24 X-REVERSIBLE COUNT [1 1 3,696,394 I Kashio Oct. 3, 1972 [54] METHOD AND ARRANGEMENT FOR 3,423,626 l/ 1969 Bouchard et a]. ..340/324 GENERATING TRACING SIGNALS 3,493,732 2/1970 Zeheb ..340/324 3,248,725 4/1966 Low et al ..340/324 [72] Invent Kashm Japan 3,587,083 6/1971 Tubinis ..340/324 A [73] Assignee: Casio Computer Kabushiki Kaisha,

Tokyo, Japan Primary Examiner-John W. Caldwell Assistant ExaminerMarshall M. Curtis [22] y Attorney-Nelson H. Shapiro [21] Appl. No.: 882,057

[57] ABSTRACT [30] Foreign Application Priority Data Tracing signals are applied to control the vertical and horizontal deflecting electrodes for a display or Dec. 11, 1968 Japan ..43/90203 recording device to reproduce modimemiona] characters or indicia. In order to generate such tracing (g1. ..340/324 Signals, the arrangement is provided with a memory which stores the programs which comprise two kinds [58] Field of Search 315/18 of information, one being for setting the counters and the other being for counting input pulses up or down by the counters connected to the memory. The step- [56] References Cited wise output of each of the counters is converted by UNITED STATES PATENTS the digital-to-analog converters into analog quantities to generate tracing or control voltages to be apphed to the deflecting electrodes of the display or recording orpe d 3,510,865 5/1970 Callahan et al ..340/324 evlce 2,766,444 10/ 1956 4 Claims, 8 Drawing Figures TO DA CONVERTER 27 Y-REVERSIB COUNTER I y (SET) RESET 0 0l234lNH.+

J a. gig 5555 2O 2 ll l2 l3 l4 l5 l6 t t t t t5 t t PATENIEIIIIms I972 3.696.394

SHEET 1 0F 3 FIG. IA

4 o 0 V I o I STEP FIG. IC 00 o 0 PK; 2 (I) (2) (3) (4) (5) (e) *-STEP X-OFT Y-OuT E D-A O-A 26 CONVERTER CONVERTER T27 x-REvERsIBLE Y-REVERSIBLE COUNTER COUNTER Ix Iy (23 I i 2O-I O. 2 CLOCK 20-2 IX y y"y 'PULSE 20"3." \20 SOURCE MEMORY 20-m PULSE OIvIOER 22 2|- I z a a s es n-I n SHIFT REOIsTER METHOD AND ARRANGEMENTFOR GENERATING TRACING SIGNALS The present invention relates to the generation of tracing signals and more particularly a method and arrangement for generating tracing signals for displaying or recording characters or indicia through a display or recording device.

With the advent of electronic computers, recording and display devices are widely used as output equipments so as to visually provide the processed information. The present invention may be advantageously applied to an ink jet recording device or display device utilizing a CRT for electronically recording or displaying the characters or indicia upon a recording or displaying medium.

In the case of recording or displaying characters or indicia by use of an ink jet recording device or cathoderay tube, the outline of the character or indicium is generally resolved into the x and y components, and the sweep voltages corresponding to the x and y components are applied to the horizontal and vertical deflecting electrodes for recording or displaying the character or indicium.

In the conventional method for generating the horizontal or X-axis and vertical or Y-axis sweep voltages, the sweep voltage of each of the characters or indicia to be displayed or recorded is obtained by quantizing each character to be converted into signals representing the instantaneous values. The signals are stored in the memory and read out therefrom for display. For this purpose, it is required to store direct current signals having various different levels, so that the memory becomes complex in construction and expensive to manufacture and encounters the difficulties of reliability and stability in operation.

Accordingly, one of the objects of the present invention is to generate the tracing signals for tracing or displaying two-dimensional characters or indicia by use of memory means simple in construction.

Another object of the present invention is to generate continuously varying tracing signals in spite of the fact that two-dimensional charactersor indicia are resolved into the X-axis and Y-axis components in a matrix array and then each of the resolved components is quantized or stepped to store the stepped components. I

Another object of the present invention is to provide a tracing signal generating arrangement of the type in which a two-dimensional character is resolved into the X-axis and Y-axis components in the coordinate system and each of the components is further stepped, each component being composed of one or more unit steps, and which has a memory which stores the information representative of the initial values of the stepped components and the information representative of the increment or decrement relative to each of the preceding stepped components.

Another object of the present invention is to provide a tracing signal generating arrangement having a memory which contains programs comprising the infor mation representative of the initial values of the X-axis and Y-axis components which were stepped or quantized with respect to the time base and information representative of the increment or decrement with respect to each of the preceding stepped or quantized components.

Another object of the present invention is to provide a tracing or display signal generating arrangement comprising a memory, X-axis "and Y-axis counter circuits which are set by the initial setting value information read out from the memory and which perform the counting operation in response to the add or subtract information representativeof the increase or decrease, and digital to-analog converters for converting the outputs of said counter circuits into analog quantities to generate analog output signals for the horizontal and vertical deflections.

Another object of the present invention is to provide an improved and novel method for generating tracing or display signals representative of two-dimensional characters or indicia.

Another object of the present invention is to provide a novel tracting or display signal generating method comprising the steps of resolving a two-dimensional character or indicium into the .X-axis and Y -axis components of the coordinate system, stepping or quantizing each of said components with respect to the time base, each component consisting of one or more unit steps, storing the information representing the initial setting value of the stepped component and the information representing the increase or decrease with.

respect to each of the preceding adjacent stepped components, reading out the content of the memory in response to a display instruction, and generating output signals for composing the two-dimensional character or indicium in response to the read out information.

According to one aspect of the present invention, a two-dimensional character or indicium to be recorded or displayed is resolved into the X-axis and Y-axis components in the coordinate system; each of the components is further stepped or quantized relative to the time base, each component consisting of one or more unit steps; and the information representing the initial setting value of the stepped component and the information representing the increment or decrement relative to the preceding stepped component are stored in a memory. As a result, the memory used in the present invention becomes very simple in construction. According to another aspect of the present invention, the memory stores programs comprising the information representing the initial setting values of the stepped components and information representing the increment or decrement with respect to the preceding stepped components. Therefore, the memory becomes simple in construction and in addition the read-out operation may be remarkably simplified.

According to another aspect of the present invention, each of the two counter circuits is set in response to the initial setting value information read out from the memory and counts a plurality of input pulses in response to the add or subtract instruction read out from the memory during the read-out signal cycle, and each of the digital-to-analog converters converts the counted outputs into analog signals, so that, despite of the fact that the information stored in the memory is stepped, continuously varying tracing or display signals may be generated.

According to another aspect of the present invention, the continuously varying tracing or display signals are generated in response to the information read out from the memory, so that a two-dimensional character or indicium may be smoothly composed under the control of the tracing or display signals.

According to another aspect of the present invention, it is not required to store in the memory the digital signals, as they stand, which represent the components of the sweep voltage. It is only required to store in the memory the information representing the initial setting values and the information representing the increment or decrement. Thus, the construction of the memory may be simplified and the sweep voltage derived from the arrangement of the present invention can continuously vary.

According to another aspect of the present invention, the tracing or display signal generating arrangementis very simple in construction and inexpensive to manufacture and the reliability and stability of the arrangement in operation are remarkably improved. Thus the arrangement of the present invention is best suitable for use with various devices for displaying or recording various characters or indicia. According tov another aspect of the invention, characters or indicia are represented as combinations of the points arrayed in the x-y matrix, and the combinations of the points are resolved into X-axis and Y-axis components to store in the memory only. the information representing the initial setting values and the information representing the increase or decrease with respect to adjacent preceding components. Therefore, the cost of the memory can be reduced.

The above and other objects, aspects and advantages of the present invention will become more apparent from the following description of illustrative embodiments thereof with reference to the accompanying drawing, in which FIGS. 1A, 1B and 1C are graphic diagrams for explanation of preparationof a program for generating a tracing or display signal,

FIG. 2 is a block diagram of one embodiment of a tracing signal generating arrangement in accordance with the presentinvention,

FIG. 3 is a circuit diagram of one embodiment of a pulse divider and a shift register shown in FIG. 2;

FIG. 4 is a circuit diagram of a memory advantageously applicable to the present invention, together with reversible counters;

FIG. 5 is a circuit diagram of reversible counters and digital-to-analog converters advantageously applicable to the present invention; and

FIG. 6 is a timing chart of the illustrated embodiment of the tracing signal generating arrangement in accordance with the present invention.

Prior to the description, the terms used in the specification are defined. The term character implies all indicia including alphanumerics and symbols. The term tracing signal is a control signal for sweeping electron beams or controlling an ink jet to be ejected from a writing head for recording or displaying.

Referring to FIG. 1 an example of the programs employed in the present invention for generating the tracing signals is shown on the coordinate. In FIG. 1A, the. characters or indicia are represented by the combinations of fifteen dots or points'arranged in a matrix array, with three columns 0, l and 2 each consisting of five points being arrayed on the X-axis or abscissa and five rows 0, l, 2, 3 and 4 each consisting of three points being arranged on the y-axis or ordinate. For example, when it is desired to display the numeric l it may be represented by the combination of six steps shown in Table 1 as set forth below.

For programming purpose, as shown in FIG. 1B the steps from (I) to (6) are plotted along the time base or horizontal axis while the voltages to be applied whose amplitude is varied in accordance with the numerals at line X shown in Table l are plotted'along the vertical axis. On the other hand, as shown in FIG. 1C, the steps from (I) to (6) are plotted along the time base or horizontal axis while the voltages to be applied whose amplitude is varied in accordance with the numerals at line Y shown in Table l are plotted along the vertical axis. Thus the horizontal and vertical sweep voltages or voltage waveforms may be obtained. As seen from Table l, the horizontal and vertical sweep or deflecting voltages are varied one by one in unit so that it is not necessary to store in a memory all of the numerals in the steps from (1) to (6) in Table 1 when a program for sweep or deflecting voltage is prepared. That is, .as shown in Table 2, it is only necessary to store the initial numerical values representative of the initial voltages to be set by the first step l) and one of three signs and 0 in each step from the second step (2) to the sixth step (6). The sign means that unit voltage is added to the initial voltage in the first step or to the voltage in the preceding step; the sign means that unit voltage is subtracted from the initial voltage set by the first step or from the voltage in the preceding step; and the sign 0 means that no voltage is added or subtracted, that is, the initial voltage or the voltage in the preceding step remains unchanged.

TABLE 2 Steps (1 Therefore, it is seen that only. a small capacity memory is required for storing the programs of the sweep or deflecting voltages. Thus, the memory for use in the present invention can be made remarkably simple in construction.

FIG. 2 is a block diagram of one embodiment of a tracing signal generating arrangement in accordance with the present invention. Memory 20 has a plurality of input terminals 20-1, 20-2, 20-m to which are applied the instruction signals specifying characters or indicia to be displayed or recorded. In the instant embodiment, m input terminals are illustrated, but the number may be increased or reduced in accordance with the number of characters or indicia desired to be displayed or recorded. To the memory 20 is connected a shift register 21 for applying pulse signals to the memory 20 from the output terminals t to t,,. As will be described in more detail hereinafter, in the memory 20, the input conductors to which are applied the display instruction signals from the input terminals 20-1 to 20-m and the input conductors to which are applied the pulse signals from the register 21 are arrayed in matrix so that programs constructed in a manner as described with reference to FIG. 1 are stored.

The shift register 21 is connected to a clock pulse source through a pulse divider 22 and a train of pulses generated by the clock pulse source 23 is divided by the pulse divider 22. In the instant embodiment, the pulse repetition rate is counted down to one fifth as will be described in more detail hereinafter. The counted down pulses are applied to the shift register 21 as shift pulses.

To the memory 20 are connected an X-reversible counter 24 and an Y-reversible counter 25 both of which are adapted to read out the content in the memory 20. The clock pulses from the clock pulse source 23 are applied to both of the X- and Y-reversible counters 24 and 25 so that the clock pulses may be counted in response to the instruction read out from the memory 20.

More specifically, the X-axis initial setting output terminal Ix and the add and subtract instruction output terminals +x and x for each step of the memory 20 are connected to the set signal input terminal Ix, the add instruction input terminal and the subtract instruction input terminal of the X-reversible counter 24, respectively. In a similar manner, the Y-axis initial setting output terminal ly and the add and subtract instruction output terminals +31 and y are connected to the set signal input terminal ly and the add and subtract instruction input terminals and of the Y-reversible counter 25, respectively.

The X- and Y-reversible counters 24 and 25 which are adapted to output the counted values corresponding to the X-axis and Y-axis sweep voltages are connected to digital-to-analog converters 26 and 27, respectively. That is, the output terminal of the X- reversible counter 24 is connected to the input terminal of D-A converter 26 whereas the output terminal of the Y-reversible counter 25 is connected to the input terminal of D-A converter 27. The output terminals of the D-A converters 26 and 27 are connected to the X-axis and Y-axis sweep voltage output terminals X-out and Y-out respectively.

Next, the mode of over-all operation of the tracing signal generating arrangement constructed as described above will be described hereinafter with reference to FIG. 2. In the memory 20 are stored the programs for displaying or recording the characters or indicia, which programs are prepared in a manner described with reference to FIG. 1, that is, the programs comprising information for initial conditions in the first step and information for addition or subtraction of the unit voltage. The pulses generated by the clock pulse source 22 are counted down to 1/P (in the instant embodiment, 1/5) and then applied to the input terminal of the shift register 21. Therefore, from the output terminals t, to t,, of the shift register 21 are derived sequentially the output pulses corresponding to the output pulses from the pulse divider 22 so as to be applied to the memory 20. To the X- and Y-reversible counters 24 and 25 are applied directly the clock pulses from the clock pulse source 23 so that to the X- and Y- reversible counters 24 and 25 are applied pulse signals the pulse repetition rate of which is P times as much as that of the pulses applied to the shift register 21.

When the display or recording instruction is applied to one of the input terminals 20-1 to 20-m of the memory 20 to select the character or indicium to be displayed or recorded, the signals representative of the initial setting values of the X- and Y-reversible counters are read out from the memory 20 at the first output pulse derived from the output terminal t, of the shift register 21. Thus, the above signals are applied to the setting signal input terminals of the X- and Y-reversible counters 24 and 25 respectively. The X- and Y-reversible counters 24 and 25 are prohibited from counting operation during the first step setting period as will be described in more detail hereinafter.

Next the output from the output terminal t of the shift register 21 is extinguished and the second pulse is derived from the output terminal t for the second step. Therefore, the instruction signals representative of the count up or count down of the set voltages in the second step are read out from the memory 20 and applied to the add or subtract instruction terminals or of the reversible counters 24 and 25.

When the signal is applied to the add instruction terminal of each of the X- and Y-reversible counters 24 and 25, the clock pulses applied thereto are sequentially counted up and added to the initial condition values, thereby increasing the counted values by a predetermined rate or increment. On the other hand, when the subtract instruction is applied to the terminal the clock pulses are sequentially counted down and subtracted from the initial condition values, thereby decreasing the counted values by a predetermined rate or decrement. When the X- and Y-reversible counters 24 and 25 add or subtract P clock pulses (in the instant embodiment, five pulses), the third output pulses are derived from the terminal t of the shift register 21 so that the content of the third step setting program is read out from the memory 20 and then applied to the X- and Y-reversible counters 24 and 25 When the content of the memory for the third step is the add instruction the number of P pulses is added to the preceding counted value. On the other hand, if the content is the subtract instruction, the number of P pulses is subtracted from the preceding counted value. When the content is 0", no addition or subtraction is carried out and the preceding counted value is held or remains unchanged.

The program of the sweep voltage for displaying or recording a character or indicium selected by applying the instruction to one of instruction input terminals of the memory 20 is read out therefrom in response to the output pulses derived from the shift register 21 and then applied to the X- and Y-reversible counters 24 and 25. Thus, in response to the output pulses from the shift register 21, the programs for the steps from l) to (6) in Table 2 are sequentially read out from the memory 20 and then applied to the X- and Y-reversible counters 24 and 25 so that the counted values of the X- and Y-reversible counters 24 and 25 continuously increase or decrease stepwisely in accordance with the unit voltages on the X-axis and Y-axis shown in the steps l) to (6) in Table l. The outputs from the X- and Y-reversible counters are applied to the D-A converters 26 and 27 respectively, thereby converting into the the analog signals. Thus, continuously varying X-axis and Y-axis tracing voltages as shown in FIGS. 18 and 1C may be obtained.

The pulse repetition rate of the pulses applied to the reversible counters 24 and 25 is P times as much as that of the pulses applied to the. memory 20, so that despite the fact that the signals are intermittently read out from the memory 20, the outputs from the X- and Y-reversible counters 24 and Y25 continuouslyvary in very small increments or decrements in stepwise. Therefore, continuous tracing or sweep voltages may be obtained only by converting the outputs from the reversible counters 24 and 25. In the above discussion, the general construction and mode of operation of the tracing signal generating arrangement in accordance with the present invention has been described. A more specific embodiment of the present invention will be described with reference to FIGS. 3 to 5 illustratingthe block diagram shown in FIG. 2 in more detail. For simplicity of the discussion, the description is directed to the case in which the alphanumeric 1 shown in FIG. 1A is displayed or recorded. It will be readily understood that other characters or indicia may be displayed or recorded in a similar manner. FIG. 3 shows a circuit diagram of one embodiment of the pulse divider 22 and shift register 21. The pulse divider comprises five stages of a two-phase dynamic register 31 and an OR gate 32. The shift register 21 comprises the n stages of a two phase dynamic register 33,an OR gate 34 andan AND gate 35. Both of the shift register 21 and the pulse divider 22 are connected to the pulse source 23 in such a manner thatthe pulses having different phases and d), may be applied to them respectively. The pulses of (b, and 4: are shown in FIG. 6(a) and are preferably out of phase by 180 relative to each other. In operation, when a trigger input is once applied to the input terminal 8,, the register 31 writes the input by the clock pulses d), and reads out the input by the clock pulses 41 so that the readout outputs are sequentially shifted into the next stages by the successive clock pulses d), and outputs are readout by 41 in sequence. When the readout output is transferred. to the final register PS, the pulse as shown in FIG.6(b) is derived from the terminal PD and the readout output is appliedto the OR gate 32 and the output continues to be circulated. The output of the pulse divider 22 is applied to one terminal of the AND gate 35 to open the AND gate together with the clock pulse (b, to provide the clock pulse for driving the two-phase dynamic register 33 of the shift register 21. When a trigger input with a suitable timing is applied to the input terminal S the input is written into the first stage and the pulses each having pulse width equal to one cycle of the output pulse from the pulse divider 22 with the timing relation as shown in FIGS.6(c) to (e) are derived sequentially and circulated in the same mode as described with reference to the pulse divider 22. That is, from the output terminals 1, to i are sequentially derived the output pulses as shown in FIGS. 6(0) to (e) and these pulses are sequentially applied to the memory 20 shown in FIG. 4. FIG. 4 illustrates one embodiment of the memory 20, together with the counters 24 and 25, with a particular diode matrix for displaying or recording the alphanumeric l in accordance with the program of the sweep voltage shown in Table 2. The other diode matrixes for displaying other characters or indicia may be arranged accordingly, but are not shown .in FIG. 4. It is also understood that instead of the diode matrixes, other suitable means such as transistor matrixes may be employed as is well known by those skilled in the art. In the memory 20 illustrated in FIG. 4, a plurality of row conductors which are connected with the input terminals 20-1 to 20-m respectively and a plurality of column conductors which are connected to the input terminals t, to t, to which are applied the inputs from the shift register 21 are array to provide the matrix. At the crosspoints of the matrix are disposed the diodes D D D and so on. The outputs of the diodes other than diodes D and D are collected to the OR gate 41 the output terminal of which is connectedto the subtract instruction input terminal of the Y-reversible counter 25. Also the output of the OR gate 41 is applied to one terminal of an AND gate 44 through an inverter 43 and the output of the AND gate 44 is applied to the inhibit input terminal INILof the X-reversible counter 24. The other input terminal of the AND gate 44 is connected to the diode D through an inverter 42. The output of the inverter 42 is also applied to the inhibit input terminal INH. of the Y-reversible counter 25.

The memory shown in FIG. 4 stores the program described with reference to FIG. 1. That is, when the input pulse t is applied from the shift register 21, the reversible counter 24 is set to zero. This means that there is no input pulse so that no wiring is required in practice. The reversible counter 25 is set to the initial value of 3 and each counter. is prohibited from counting. At the input pulse t the add instruction is given to the reversible counter 24 and to the counter 25 so that each of the counter starts counting up P clock pulses (in the instant embodiment, five clock pulses). Upon arrival of the input pulse t the reversible counter 24 is prohibited or held while the subtract instruction is given to the reversible counter 25, thereby starting the subtraction. Upon arrival of the input pulses t t and t the reversible counter 24 is still prohibited or held, whereas to the reversible counter 25 is given sequentially the subtract instructions so that the reversible counter 25 continues to count down the pulses In the memory 20 is stored such program that gives the instructions described hereinabove.

, FIG. 5 is a circuit diagram of the reversible counters and digitalto-analog converters. Since the reversible counter 25 has the same construction as that of the reversible counter 24, the former is illustrated by the simplified block. Similarly, the D-A converter 27 has the same construction as that of the converter 26, so that the former is illustrated in a block form. As shown in FIG. 4, the reversible counter 24 has the highest initial set of 2, it has three set input terminals 0,1 and 2. The reversible counter 25 has the highest initial set of 4, it has five set signal input terminals 0,1,2,3 and 4. It is noted that it is not required to apply the setting signal to the terminal 0 of each of the reversible counters, so that no terminal 0 and wiring therefor are provided in practice. It is also important to note that when the input is applied to the setting signal input terminal 3 of the counter, the count 15 is set in the instant embodiment and the counting is started therefrom.

In the reversible counter shown in FIG. 5, reference characters FF-l, FF-2, FF-n designate .IK flipflops; AU-l, AU-2, AU-n designate AND gates which are selectively operated when the add instruction is applied; AD-l, AD 2, AD-n designate AND gates which are selectively operated when the subtract instruction is applied; -1, 0-2, 0-n designate OR gates for driving the next stages; 0 0, O designate OR gates for applyingreset inputs; 0, designates an input OR gate and A, designates an input AND gate. Therefore, the reversible counter 24 functions as an adder or subtractor depending upon whether the add instruction ADD or the subtract in struction SUBTRACT is applied from the memory 20 so as to open the AND gates AU-l to AU-n or the AND gates AD-1 to AD-n. That is, the reversible counter 24 is a binary counter consisting of JK flipflops to which are applied from the clock pulse source 23 the clock pulses (I), anddi which have a phase relation as shown in FIG. 6-(a). To each stage of the reversible counter 24 is applied the add and subtract instructions from the memory 20 while to the initial stage of the reversible counter 24 is applied the inhibit instruction. The counted values are readout from the JK flipflops which constitute the respective stages of the reversible counter 24 by each clock pulse and then applied in parallel to the stages of the digital-to-analog converter 26. I

The digital-to-analog converter 26 shown in FIG. is of a well known ladder type and is composed of n stages of circuits. The circuit in each stage comprises resistors R or R/2 each having a suitable resistance and MOS transistors T and T The transistors T and T in each stage are connected to the weighted outputs Q and 6 of the JK flip-flop of each stage of the reversible counter and are controlled by the input from the counter so that the potential on the adder input at the point a in each stage may be selected to 0 volt or -E volt. No further description of the digital to-analog converter consisting of a ladder type circuit will be made as it'is well known by those skilled in the art. Next the mode of operation will be described with reference to FIGS. 3 to 6. For the sake of description, the signals displaying or recording the alphanumeric l shown in FIG. 1 are assumed to be generated and the clock pulses 5 and (b are counted down to l/5 in pulse repetition rate by the pulse divider 22. It is further assumed that all of the circuits are reset and no clock pulse is generated prior to the operation. When the instruction illustrated in FIG. 6(/) is applied to the alphanumeric display instruction terminal -1 in FIG. 4, the clock pulses d), and are applied to the reversible counters 24 and and the pulse divider 22 which generates the pulses as shown in FIG. 6(b). In this case, the reversible counters 24 and 25 will not count the clock pulses during the first pulse T shown in FIG.6(c). When the pulse output T is derived from the terminal t register 21, the output of the diode D is applied to the setting signal input terminal 3 of the reversible counter 25 so that the reversible counter 25 is the reversible to the count 15. Simultaneously, the output of the diode D is applied to the inverter 42 so that the AND gate 44 is prohibited. The output of the AND gate is applied to the inhibit terminal INI-I. of the reversible counter 24 so that the latter is prohibited from counting the pulses during the pulse T The output of the inverter 42 is also applied to the inhibit terminal INH. of the reversible counters 25 so that the latter is prohibited from counting the pulses. In the next step, the diode D provides the output pulse T (shown in FIG.6(d)) from the terminal of the shift register 21 and the output of the diode D is applied to the add instruction input terminal of each of the reversible counters 24 and 25 so that the reversible counter is selected to function as adder or count-up counter. In-this state, the counter 24 counts up during the selected period of the second step (the pulse width T the pulses as 1,2,3,4 and 5 from the count 0. On the other hand, the counter 25 counts up during the selected period of the second step the pulses as 16, 17, 18, 19 and 20 from the count 15. In the third step upon generation or arrival of the pulse T the output is derived from the diode D and is applied to the subtract instruction terminal or SUBTRACT of the reversible counter 25 through the OR gate 41, so that the counter 25 is selected to function as a subtractor or count-down counter. In this state, the counter 25 counts down, during the selected period of the third step, from the count 20 of the preceding or second step, l9, 18, 17, 16 and 15. The output of the OR gate 41 is applied also to the inverter 43 so that the output of the inverter 43 prohibits the AND gate 44 during the third step period or the width of the pulse T thereby inhibiting the counting of the reversible counter 24. This means that the content of the counter 24 remains unchanged. Similarly in the fourth step and so on, the content 5 of the reversible counter 24 remains unchanged until the final or sixth step. In the reversible counter 25, the subtractioncontinues so that in the 4th step, the content is counted down to l0; in the fifth step, to 5; and in the6th step, to 0. Thus, the program shown in Tables 1 and 2 is executed. At each of the clock pulses (1) the counted values from the reversible counters 24 and 25 are applied to the digital to-analog converters 26 and 27 respectively which in turn provide the outputs X-OUT and Y-OUT, which vary substantially linearly as shown in FIGS. 18 and 1C, to the horizontal and vertical deflecting electrodes (not shown) respectively as tracing or control signals. Thus, the alphanumeric 1 as shown in FIG. 1A is displayed or recorded.

The present invention has been so far described with specific reference to the illustrative embodiments thereof, but it will be understood that variations and modifications can be effected without departing from the true spirit of the present invention. For example, for the sake of understanding, each element of the circuits has been shown as being discrete, but integrated circuits, modules, etc. may be employed in the present invention.

Iclaim:

1. In apparatus for composing characters in accordance with X and Y coordinates tracing signals, the combination comprising X and Y up-down pulse counters, pulse generating means connected to said counters for generating pulses of predetermined repetition rate to be counted by said counters, digital-to-analog converter means connected to said counters for converting digital outputs of said counters to analog X and Y tracing signals, and counter control means for causing said counters to set initially and to count up or count down by discrete increments or decrements in 1! response to said pulses, or not to count, in accordance with successive portions of characters to be composed, the counter control means comprising memory means for providing control signals for controlling the initial setting of said counters and the up or down counting of said counters, selection means connected to said memory means for selecting control signals to be supplied to said counters in accordance with a selected character to be composed, and timing means con-.

nected to said memory means for causing the selected control signals to be supplied to said counters during successive intervals corresponding to portions of the selected character to be composed. I

2. Apparatus in accordance with claim 1, wherein 

1. In apparatus for composing characters in accordance with X and Y coordinates tracing signals, the combination comprising X and Y up-down pulse counters, pulse generating means connected to said counters for generating pulses of predetermined repetition rate to be counted by said counters, digital-to-analog converter means connected to said counters for converting digital outputs of said counters to analog X and Y tracing signals, and counter control means for causing said counters to set initially and to count up or count down by discrete increments or decrements in response to said pulses, or not to count, in accordance with successive portions of characters to be composed, the counter control means comprising memory means for providing control signals for controlling the initial setting of said counters and the up or down counting of said counters, selection means connected to said memory means for selecting control signals to be supplied to said counters in accordance with a selected character to be composed, and timing means connected to said memory means for causing the selected control signals to be supplied to said counters during successive intervals corresponding to portions of the selected character to be composed.
 2. Apparatus in accordance with claim 1, wherein said timing means comprises means connected to said pulse generating means for applying control signal read-out pulses to said memory means at a rate which is a fraction of the said repetition rate.
 3. Apparatus in accordance with claim 1, said apparatus comprising X and Y trace deflecting electrodes to which the corresponding tracing signals are applied.
 4. Apparatus in accordance with claim 1, wherein said memory means comprises a matrix having two sets of input terminals, one of which is connected to said selection means and the other of which is connected to said timing means. 